WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

THE ROLE:

As an AMD Graphics IP (GXIP) RAS Engineer, you will work at the intersection of GPU and MI accelerator architecture and Reliability, Availability, and Serviceability (RAS) requirements. This role is designed for a strong mid-level engineer who is interested in system reliability and wants to grow into a RAS architecture role.

You will work closely with experienced GFXIP, AI, and RAS architects to help design, analyze, and improve RAS features for next-generation AMD products across data center, client, and automotive markets. Through hands-on participation and mentorship, you will build expertise in RAS concepts, architectural tradeoffs, and hardware reliability.

This role provides exposure to real production silicon, cross-functional collaboration, and increasing technical ownership as your RAS experience grows.

THE PERSON

You are a solid engineer with a strong technical foundation who is interested in system robustness and reliability. You are comfortable working across disciplines, asking questions, and learning from more experienced engineers. You communicate clearly, value collaboration, and are motivated to develop deeper architectural skills.

You do not need to be a RAS expert on day one—curiosity, fundamentals, and growth mindset matter more than prior RAS ownership.

KEY RESPONSIBILITIES:

• Contribute to the definition and development of RAS features and capabilities for next-generation GFXIP deployments.
• Assist in writing and reviewing architectural specifications related to RAS features.
• Work with senior RAS and GFXIP architects to learn and apply reliability concepts, including error detection, containment, recovery, and reporting.
• Help analyze and understand reliability metrics such as FIT, DPPM, MTBF, and MTBR, and how they trade off against performance, power, area (PPA), and security.
• Support hardware design teams in evaluating RAS protection and coverage, and in identifying gaps or improvement opportunities.
• Collaborate across SoC, RAS, and business teams to ensure RAS requirements are understood and correctly implemented.
• Experience designing, analyzing, or implementing hardware or system features in VLSI-based designs.
• Solid understanding of digital logic, computer architecture, and hardware design fundamentals.
• Ability to read and reason about specifications, RTL, and architectural documentation.
• Good communication skills and ability to work in cross-functional engineering teams.

PREFERRED EXPERIENCE:

• Exposure to or interest in reliability, fault tolerance, or system-level robustness.
• Familiarity with RAS-related concepts or mechanisms such as: Parity and ECC, Watchdog timers, Heartbeat monitors, Deferred or recoverable error handling
• Background in GPU architecture.
• Experience with RTL design and/or verification.
• Interest in understanding failure rates and figures of merit.

• Exposure to AI/ML accelerator architectures and AI compute environments.
• Interest in reliability challenges in large-scale AI systems and accelerator deployments.

ACADEMIC CREDENTIALS:

• Undergrad degree required. Bachelors, Masters or PhD degree in Computer Engineering/Electrical Engineering preferred.

This role is not eligible for visa sponsorship.

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Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.

As an AMD Graphics IP (GXIP) RAS Engineer, you will work at the intersection of GPU and MI accelerator architecture and Reliability, Availability, and Serviceability (RAS) requirements. This role is designed for a strong mid-level engineer who is interested in system reliability and wants to grow into a RAS architecture role. You will work closely with experienced GFXIP, AI, and RAS architects to help design, analyze, and improve RAS features for next-generation AMD products across data center, client, and automotive markets. Through hands-on participation and mentorship, you will build expertise in RAS concepts, architectural tradeoffs, and hardware reliability. This role provides exposure to real production silicon, cross-functional collaboration, and increasing technical ownership as your RAS experience grows. THE PERSON - You are a solid engineer with a strong technical foundation who is interested in system robustness and reliability. You are comfortable working across disciplines, asking questions, and learning from more experienced engineers. You communicate clearly, value collaboration, and are motivated to develop deeper architectural skills. You do not need to be a RAS expert on day one—curiosity, fundamentals, and growth mindset matter more than prior RAS ownership. KEY RESPONSIBILITIES: Contribute to the definition and development of RAS features and capabilities for next-generation GFXIP deployments. Assist in writing and reviewing architectural specifications related to RAS features. Work with senior RAS and GFXIP architects to learn and apply reliability concepts, including error detection, containment, recovery, and reporting. Help analyze and understand reliability metrics such as FIT, DPPM, MTBF, and MTBR, and how they trade off against performance, power, area (PPA), and security. Support hardware design teams in evaluating RAS protection and coverage, and in identifying gaps or improvement opportunities. Collaborate across So. C, RAS, and business teams to ensure RAS requirements are understood and correctly implemented. Experience designing, analyzing, or implementing hardware or system features in VLSI-based designs. Solid understanding of digital logic, computer architecture, and hardware design fundamentals. Ability to read and reason about specifications, RTL, and architectural documentation. Good communication skills and ability to work in cross-functional engineering teams. PREFERRED EXPERIENCE:Exposure to or interest in reliability, fault tolerance, or system-level robustness. Familiarity with RAS-related concepts or mechanisms such as: Parity and ECC, Watchdog timers, Heartbeat monitors, Deferred or recoverable error handling. Background in GPU architecture. Experience with RTL design and/or verification. Interest in understanding failure rates and figures of merit. Exposure to AI/ ML accelerator architectures and AI compute environments. Interest in reliability challenges in large-scale AI systems and accelerator deployments. ACADEMIC CREDENTIALS: Undergrad degree required. Bachelors, Masters or PhD degree in Computer Engineering/ Electrical Engineering preferred. This role is not eligible for visa sponsorship. #LI-BM 1#LI-Hybrid

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