Senior ASIC Design Engineer
Dallas, TX
Updated: May 07
job summary: Seeking a Senior ASIC Design Engineer for a high growth defense contractor in the Dallas, TX area. The Senior Design Engineer will be responsible for leading the development of next-generation Image Processing SoCs. In this role, you will be responsible for architecting, designing, and implementing complex Verilog/SystemVerilog blocks that power high-performance thermal imaging systems. Experience with SoC/CPU/GPU architecture, AXI inter
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- RTL Development: Design and implement complex logic blocks in Verilog/SystemVerilog for real-time image processing pipelines.\n\t
- Architecture Integration: Integrate SoC components including CPUs, GPUs, and specialized NPU/ISP cores, ensuring seamless communication via AXI/AHB interconnects.\n\t
- High-Speed Design: Develop high-speed interfaces and implement techniques for managing high-bandwidth memory traffic (DDR/LPDDR) to support high-resolution sensor data.\n\t
- Performance Optimization: Conduct area, power, and timing analysis to meet the stringent SWaP (Size, Weight, and Power) requirements of tactical electro-optical systems.\n\t
- Verification Collaboration: Work closely with the DV team to develop functional coverage models and debug complex issues within a UVM (Universal Verification Methodology) environment.\n\t
- Mentorship: Provide technical leadership to junior engineers and contribute to the evolution of internal design standards and IP libraries.\n
#LI-DC2
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- Experience level: Experienced
- Minimum 8 years of experience
- Education: Bachelors (required)
Seeking a Senior ASIC Design Engineer for a high growth defense contractor in the Dallas, TX area. The Senior Design Engineer will be responsible for leading the development of next-generation Image Processing SoCs. In this role, you will be responsible for architecting, designing, and implementing complex Verilog/ System. Verilog blocks that power high-performance thermal imaging systems. Experience with So. C/ CPU/ GPU architecture, AXI inter[ "\n\t. RTL Development: Design and implement complex logic blocks in Verilog/ System. Verilog for real-time image processing pipelines.\n\t. Architecture Integration: Integrate So. C components including CP - Us, GP - Us, and specialized NPU/ ISP cores, ensuring seamless communication via AXI/ AHB interconnects.\n\t. High-Speed Design: Develop high-speed interfaces and implement techniques for managing high-bandwidth memory traffic (DDR/ LPDDR) to support high-resolution sensor data.\n\t. Performance Optimization: Conduct area, power, and timing analysis to meet the stringent S - Wa. P (Size, Weight, and Power) requirements of tactical electro-optical systems.\n\t. Verification Collaboration: Work closely with the DV team to develop functional coverage models and debug complex issues within a UVM (Universal Verification Methodology) environment.\n\t. Mentorship: Provide technical leadership to junior engineers and contribute to the evolution of internal design standards and IP libraries.\n\n\n#LI-DC 2\n" ][ "Experience level: Experienced. Minimum 8 years of experience. Education: Bachelors (required)" ]
search terms: Design Engineer+Engineer
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